ABC80/max80_fw @ 06f36dc8f04367574ee87218b014e89e81fb390c

H. Peter Anvin 06f36dc8f0 Merge remote-tracking branch 'origin/main' into slow		3 rokov pred
..
ip	06f36dc8f0 Merge remote-tracking branch 'origin/main' into slow	3 rokov pred
output	06f36dc8f0 Merge remote-tracking branch 'origin/main' into slow	3 rokov pred
scripts	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	3 rokov pred
simulation	f24cac3c43 fpga: lint code to make ModelSim RTL simulation work again	3 rokov pred
usb	808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs	3 rokov pred
.gitignore	344ccf56d4 Fixes for dual version generator	3 rokov pred
Makefile	6db45e74e6 WIP: build both v1 and v2	3 rokov pred
abcbus.sv	81633591fa v2: abc_host and abc_a_oe are redundant and unified in v2	3 rokov pred
assignment_defaults.qdf	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	3 rokov pred
clkbuf.sv	808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs	3 rokov pred
fast_mem.sv	dd69eafb99 Many timing fixes; better IRQ handling for abcbus	3 rokov pred
functions.sv	f2060589ab Default baud rate = 115200, baud rate programmable	3 rokov pred
i2c.sv	4970fb6ef6 rtc: issue dummy clock cycles if SDA appears stuck	3 rokov pred
iodevs.vh	7c7d4cd52c usb: set the device serial number	3 rokov pred
max80-v1.cof	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	3 rokov pred
max80-v2.cof	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	3 rokov pred
max80.qpf	808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs	3 rokov pred
max80.qsf	808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs	3 rokov pred
max80.sdc	60be2e1201 v2: v2 has a 16 MHz oscillator instead of 48 MHz	3 rokov pred
max80.sv	06f36dc8f0 Merge remote-tracking branch 'origin/main' into slow	3 rokov pred
picorv32.v	372899ea3b Move most code to SDRAM; fix problems with code in SDRAM; cleanups	3 rokov pred
rng.sv	de1566292f clocks: centralize strobes; rng: shut down when not in use	3 rokov pred
sdcard.sv	ec99762a84 Use waitirq rather than suspending a memory transaction for SD card	3 rokov pred
sdram.sv	63c8bc2ec8 sdram: fix signal timing that broke dram bss zeroing.	3 rokov pred
spi_master.sv	062a3d9eb1 Reorganize tree so a single Makefile can do the right thing	3 rokov pred
spirom.sv	808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs	3 rokov pred
synchro.sv	4e65673781 spirom: add support for sending arbitrary SPI commands	3 rokov pred
sysclock.sv	3dfb6626a1 More clock tree changes; fix rng oscillator sources	3 rokov pred
tmdsenc.sv	74d9da52b0 hdmi/tmds: fix symbol data ordering	3 rokov pred
transpose.sv	510e702728 video: initial simple video generator; add support for HDMI TERC4	3 rokov pred
tty.sv	6ae39aaf12 Make romcopy device programmable and able to zero memory	3 rokov pred
v1.pins	6db45e74e6 WIP: build both v1 and v2	3 rokov pred
v1.qsf	08d8d7d2c8 More cleanups of multi-version... still broken?!	3 rokov pred
v1.sv	60be2e1201 v2: v2 has a 16 MHz oscillator instead of 48 MHz	3 rokov pred
v1_description.txt	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	3 rokov pred
v2.pins	60be2e1201 v2: v2 has a 16 MHz oscillator instead of 48 MHz	3 rokov pred
v2.qsf	08d8d7d2c8 More cleanups of multi-version... still broken?!	3 rokov pred
v2.sv	92d18543b8 tty: don't require DTR#; v2: output some clocks on gpio[135]	3 rokov pred
v2_description.txt	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	3 rokov pred
video.sv	980eaf0400 Restructure clock tree; better sdram timing; random number generator	3 rokov pred